cd4029a typ s cos/mos presettable up/down counter binary or bcd-decade the rca-cd4029a consists of a four-stage 1 binary or bcd-decade up/down counter with provisions for look-ahead carry in both counting modes. the inputs consist of a single clock, carry-in (clock inhi- biti. binary/decade, up/down, pre- set enable, and four individual jam sig- nals and a car ry out signal are provided as outputs. a high preset enable signal allows information on the jam inputs to preset the counter to any state asynchronously with the clock. a iowan each jam line, when the preset-enable signal is high, resets the counter to its zero count. the counter is advanced one count at the positive transition of the clock when the carry-in and pre- set enable signals are low. advancement is inhibited when the carry-in or preset enable signals are high. the carry-out signal is normally high and goes low when the counter reaches its maximum count in the up mode or the minimum count in the down mode provided the carry-in sig- nal is low. the carry-in signal in the high state can thus be considered a clock inhibit. the carryin terminal must be connected to vss when not in use. binary counting is accomplished when the binary/decade input ishigh;the counter counts in the decade mode '.vhen the bi- nary /decade input is low. the counter counts up when the up/down input is high, and down when the up/down input features: ? medium speed operation ... 5 mhz (typ.) @ cl =15 pf and vdd-vss=10 v ? multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times ? "preset enable" and individual "jam" inputs provided ? binary or decade up/down counting ? bcd outputs in decade mode ? quiescent current specified to 15 v ? maximum input leakage current of 1 ij-a at 15 v (full packagetemperature range) ? l-v noise margin (full package- temperature range) applications: ? programmable binary and decade counting/frequency synthesizers-bcd output ? analog to digital and digital to analog conversion ? up/down binary counting ? magnitude and sign generation ? up/down decade counting ? difference counting is low. multiple packages can be connected in either a parallel-clocking or a ripple- clocking arrangement as shown in fig. 13. parallel clocking provides synchronous can trol and hence faster response from all counting outputs. ripple-clocking allows for longer clock input rise and fall times. these types are supplied in l6-lead hermetic dual-in-line ceramic packages (d and f suffixes), l6-lead dual-in-line plastic pack- age (e suffix), t6~jead cerami~jiiljlla~_k_~g~~ (k suff!!1 and in chip for"! (h suffix) recommended operating conditions at t a=25 0 c, except as noted. for maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: limits characteristic d,f,h e vod packages package (v) min. max. min. max. supplyvoltage range (for t a=full 3 12 3 12 package temperature range) setup time, ts 5 650 - 1300 - 10 230 460 - - clock pulse width, tw 5 340 - 500 - 10 170 250 - - clock input frequency. fcl 5 dc 15 dc 1 10 dc 3 dc 2 clock rise or fall time. trcl,tfcl' ? 5 - 15 - 15 10 - 15 - 15 preset enable pulse width, tw 5 330 -- 660 - 10 160 320 - - 'from up/down. binary/decode. carry in. or preset enable control inputs to clock edge **if more than one unit is cascaded in the parallel clocked appiocatlon. trcl should he m,ldp less than or equal to the sum of the f,xed propagation delay at 15 pf and the trdnsltlon time of the carry output drovlng stage for the estimated capacitive load 502 units v ns ns mhz ps ns preset enable carry in (clock inhibiti ~ binary i decade upidown 10 clock cd4029a functional diagram fig 1- tvpica/ propagation delav time vs. cl for 0 outputs. load cuacit&nc[ (c ? .i-" fig. 2- tvplca/ propagation delav time vs. c l forcarrv output. fig. 3-. tvpical transition time vi. c l for o outputs. ii
maximum ratings, absolute-maximum values storage-temperature range (t stg ) operating-temperature range (t a) package types o,f,h package type e dc supply-voltage range, (v oo ) (voltages referenced to vss terminal) power dissipation per package (po) for t a=-40 to +60 0 c (package type e) for t a=+60 to +85 0 c (package type e) for r a=-55 to +ioo o c (package types o,f) for t a =+100 to +125 0 c (package types d,f) device dissipation per output trmjsistor -55 to -+ 125c -40 to +85 0 c -05 to +15 v 500mw derate llnearlv at 12 mw/oc to 200 mw 500mw derate linearly at 12 mw/oc to 200 mw for t a=full package-temperature range (all package types) 100mw 05 to v dd +05 v input voltage range, all inputs lead temperature (during soldering) at d,stance 1/16 1/32 inch (1 59 079 mm) from case for 10 s max dynamic electrical characteristics at t a=25 0 c, input t r ,lf=20 ns, cl =15 pf, rl -200 h2 characteristic carry output minimum preset enable pulse width, tw minimum preset enable test +265 0 c units ils ns ns ps ns ns ns ns ns cd4029a types load cal'llw:itanc[icli-" fig. 4-typlcal transition time vs. c l for carry output. supply volts i voo' fig. 5- ~axlmum clock input frequency vs. voo' o vss vss 91(117'.0_ fig 6 - qulescent-devlclh:urrent i test circuit. '~i--o'~ o_~ ndtt tdt any oiit input. vss with otmfji inputs at voo orvss fig 7- noise-immunity test circuit voo inpuds voo ~ vss not[ "usur[ inputs sequ[ntially, vss to iioth voo ana v,s conn[ct all unusm inp\its to [ither voo or vss fig. 8- input-ieakage-current test c"cult _________________________________________________________________ 503
cd4029a types static electrical characteristics umits at indicated temperatures (oci characteristic conditions d,f,h packages e package vo vtn voo -55 (vi (v) (v) quiescent 5 5 - - device 10 10 current, - - - - 15 50 il max. output voltage low level, - 5 5 vol - 10 10 high level, - 0 5 voh - 0 10 noise immunity inputs low, 42 - 5 v nl 9 - 10 inputs high. 08 - 5 v nh 1 - 10 noise margin inputs low, 45 - 5 vnml 9 - 10 inputs high. 0.5 - 5 vnmh 1 - 10 output drive cur rent nchannel (sink), ion min. qoutputs 05 ... 5 05 05 - 10 074 carry out 05 - 5 01 put 05 - 10 04 pchannel (source), lop min q outputs 45 - 5 -0.18 95 - 10 -0.3 carfy out 45 - 5 -0.09 put 9.5 - 10 -015 input tint leakage - - 15 current, iiliih ~ ___ ioo 0-4~~_~f.ss wall logic inputs are: protccho by cos/mos protection network 504 6 truth tabl.e for f -f no i +25 +125 ~o +25 typ. 0.3 05 1 08 12 016 064 -0.24 -04 -0.12 -02 limit typ. umit 5 300 50 0.5 50 10 600 100 1 100 50 2000 500 5 500 o typ ,005 max. o typ .. 005 max. 4.95 min, 5 typ 995 min, 10 typ 1.5 min, 2 25 typ 3 min. 45 typ 1 5 min , 2 25 typ 3 min. 45 typ 1 min 1 min 1 min 1 min. 04 028 024 0.8 02 06 0.42 036 12 03 008 0.06 005 016 004 032 022 019 064 0.16 -012 -0.08 -0.07 -024 -0.06 -0.2 -0.14 -0.14 -0.4 -0.1 -0.06 -0.04 -0.04 -012 -0.03 -01 -0.07 -0.07 -0.2 -0.05 tl0- 5 typ., tl max " .. truth table for f-f's 2.3,4 fig. "-logic diagram. 0, 1'0 units +85 700 1400 j.la 5000 v v v 0.16 024 003 0.13 ma -0.05 -0.08 -0.02 -0.04 j.la ii fig. 9- typical dissipation charbcteristlcs. "clock down" _............. j i i i "clock" i c040lla i l ~a~i~t~n~a~-.l fig. 'o-conversion of clock up, clock down mput signals to clock and up/down input signals. the cd4029a clock and up/down inputs are used directly in most applications. in applications where clock up and clock down inputs are provided, conversion to the cd4029a clock and up/down inputs can easily be realized by use of the circuit shown below. cd4029a changes count on positive transi tions of clock up or clock down inputs. for the gate configuration shown below, when counting up the clock down input must be maintained high and conversely when counting down the clock up input must be maintained high. clock te pe j 0 0 5 0 1. 0 0 a ne j' x 0 a ne nc-nochange fe-toggle enable' ti ej _ te q cl o carry in (ell (clock inhibit) cloc tt: pe j 0 0 x x 0 0 0 i 1. 0 i x ii 0 i 0 i x 0 6 ne o 5 ne advance counter at pos clock transition
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